A semiconductor memory IC, such as a synchronous graphics random access memory (SGRAM), typically includes an array of memory cells organized into rows and columns. Each memory cell can store one bit of data and is accessed by activating a row line of the row of the memory cell and a column line or pair of column lines of the column of the memory cell. Herein, the invention is illustrated assuming that a pair of column lines is connected to each column of memory cells, without loss of generality. A memory cell access can occur in the course of a read or write operation and a row line or column line pair can be activated by applying a particular voltage to the row line or column line pair or by monitoring the voltage thereon. Each memory cell is assigned a unique address which can be divided into a row address, indicating a row line connected to the cell, and a column address, indicating a column line pair connected to the cell.
FIG. 1 shows the column decoder architecture 10 of a conventional RAM. In writing a data value to a particular accessed memory cell, the data value appearing on I/O pad 12 is inputted to a write driver 14. The data value is outputted from the write driver 14 on a pair of data lines 22 to I/O line pairs 16-1, 16-2, . . . , 16-N. The data value is provided to each of N column decoders 18-1, 18-2, . . . , 18-N to which each corresponding I/O line pair 16-1, 16-2, . . . , 16-N is connected. Each column decoder 18-1, 18-2, . . . , 18-N activates one column line pair of a set of (in this case, eight) column line pairs 20-0, 20-1, 20-2, 20-3, 20-4, 20-5, 20-6 or 20-7 which activated column line pair is connected to the particular accessed cell. The particular column line pair 20-0 to 20-7 activated is indicated by part of the column address Y of the to-be-accessed cell. (Another portion of the column address Y of the cell not shown may be used to selectively activate only the particular one of the column decoders 18-1, 18-2, . . . , 18-N connected to the set of column line pairs 20-0 to 20-7 possessing the column line pair of the accessed cell).
The SGRAM column decoder architecture 10 shown in FIG. 1 is advantageous in that a savings is achieved in layout area for the I/O lines 16-1, 16-2 and 16-N. Specifically, (other than the address lines Y) only a single pair of data lines 22 need extend along the top of the memory array.
Desirably, the column decoder architecture 10 supports a block write operation, during which a single data value is stored in multiple memory cells simultaneously. Another signal can be propagated by a line (not shown) for causing a column decoder, e.g., the column decoder 18-1, to activate all column line pairs 20-0 to 20-7 simultaneously during a block write operation, thereby storing the data value transferred via data line pair 22 in a cell of each column.
In a more advanced block write operation, a mask is externally supplied which specifies only selected ones of the columns, of a set of columns, to be written with the data value during the block write. However, the column decoder architecture 10 of FIG. 1 cannot accommodate such a maskable block write operation.
FIG. 2 shows a second conventional column decoder architecture 30 that supports a maskable block write operation. A data value appearing on the I/O pad 32 is driven by the write driver 34 onto a data line 46. The data value on data line 46, and an externally supplied mask signal CMSK, are received at a mask circuit 44. The mask circuit 44 outputs the data value of data line 46 on each pair of I/O lines 36 corresponding to a particular column line, as specified by the mask. For instance, the column line pairs are organized into N sets 41-1, . . . 41-N, of, for example, eight column line pairs per set. The mask has eight bits specifying which of the column line pairs of a set of column line pairs should be written with the data value. The mask circuit 44 outputs a copy of the data value on only those I/O line pairs 36 corresponding to column line pairs of a set indicated by the mask signal CMSK. Each copy of the data value is carried to a respective column decoder 38-1, . . . , 38-N by a corresponding set of I/O line taps 36-1, . . . , 36-N. (The column address Y is also received at the column decoders 38-1, . . . , 38-N for use in an ordinary write or read operation.) In response, the column decoders 38-1, . . . , 38-N activate the column line pairs for which data is provided so as to simultaneously store the data values into each non-masked column.
Multiple pitch column decoders, such as double pitch and quad pitch column decoders are known. Multiple pitch column decoders can save layout spacing in the area allocated to the column decoders. For example, a double pitch column decoder is connected to two sets of column line pairs and has a separate sense amplifier for each set of column line pairs. During an ordinary read or write operation to a single addressed cell, the double pitch column decoder actually selects two column line pairs, namely, one column line pair in each of the two sets to which it is connected. The particular selected column line pair in each set is indicated by a portion of the column address. However, a column select signal activates only one of the two sense amplifiers, thereby only enabling one column line pair to be activated. Likewise, a quad pitch column decoder is a decoder connected to four sets of column line pairs. The quad pitch column decoder selects four column line pairs in response to an ordinary read or write operation, namely, one column line pair in each of the four sets to which it is connected. However, one or more column select signals disable three of the four sense amplifiers of the non-selected sets of column line pairs so that only one column line pair is effectively activated.
The column decoder architecture 30 of FIG. 2 can accommodate the maskable block write operation. The problem, however, is that multiple I/O lines 36 must be provided at the top of the array that run the entire length of the array. Each I/O line requires, for example, 2 .mu.m of spacing for the width of the line and for separating adjacent lines from each other. The example in FIG. 2 shows only eight I/O line pairs 36 running across the top of the array requiring a total area of 8.times.2.times.2 .mu.m wide.times.the length of the top of the array.
It is an object of the present invention to decrease the spacing requirement necessary to implement a maskable block write operation in a semiconductor memory IC.